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<div class="header">
  <div class="summary">
<a href="#pub-attribs">Data Fields</a>  </div>
  <div class="headertitle"><div class="title">SCTLR_Type Struct Reference<div class="ingroups"><a class="el" href="group__CMSIS__core__register.html">Core Register Access</a> &raquo; <a class="el" href="group__CMSIS__SCTLR.html">System Control Register (SCTLR)</a></div></div></div>
</div><!--header-->
<div class="contents">

<p>Bit field declaration for SCTLR layout.  
 <a href="unionSCTLR__Type.html#details">More...</a></p>

<p><code>#include &lt;core_ca.h&gt;</code></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="pub-attribs" name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:ac46a564759115a014ad0fcf7c02bd679"><td class="memItemLeft" >struct {</td></tr>
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<tr class="memdesc:aec72778bd0edb8bda7b2b570ee255cfc"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 0 MMU enable  <a href="unionSCTLR__Type.html#a8cbfde3ba235ebd48e82cb314c9b9cc4">More...</a><br /></td></tr>
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<tr class="memdesc:a67bd387b197de5e7adef1efb50467029"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 25 Exception Endianness  <a href="unionSCTLR__Type.html#af868e042d01b612649539c151f1aaea5">More...</a><br /></td></tr>
<tr class="separator:a67bd387b197de5e7adef1efb50467029"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<tr class="memdesc:adbd3ce03ac1eaffc2efb86178c03fa03"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 27 Non-maskable FIQ (NMFI) support  <a href="unionSCTLR__Type.html#a60d589567422115a14d6d0fde342dfce">More...</a><br /></td></tr>
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<tr class="memdesc:a7d48d1e63751847f700e6d0d0c7a1978"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 30 Thumb Exception enable  <a href="unionSCTLR__Type.html#a25d4c4cf4df168a30cc4600a130580ab">More...</a><br /></td></tr>
<tr class="separator:a7d48d1e63751847f700e6d0d0c7a1978"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac46a564759115a014ad0fcf7c02bd679"><td class="memItemLeft" valign="top">}&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionSCTLR__Type.html#ac46a564759115a014ad0fcf7c02bd679">b</a></td></tr>
<tr class="memdesc:ac46a564759115a014ad0fcf7c02bd679"><td class="mdescLeft">&#160;</td><td class="mdescRight">Structure used for bit access.  <br /></td></tr>
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<tr class="memitem:a4cb084e09742794f1d040c4e44ee4e0f"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionSCTLR__Type.html#a4cb084e09742794f1d040c4e44ee4e0f">w</a></td></tr>
<tr class="memdesc:a4cb084e09742794f1d040c4e44ee4e0f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Type used for word access.  <br /></td></tr>
<tr class="separator:a4cb084e09742794f1d040c4e44ee4e0f"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<div class="textblock"><p>Bit field declaration for SCTLR layout. </p>
</div><h2 class="groupheader">Field Documentation</h2>
<a id="a078edcb9c3fc8b46b8cf382ad249bb79" name="a078edcb9c3fc8b46b8cf382ad249bb79"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a078edcb9c3fc8b46b8cf382ad249bb79">&#9670;&#160;</a></span>A</h2>

<div class="memitem">
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      <table class="memname">
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<p>bit: 1 Alignment check enable </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ae5a729bf64a6de4cbfa42c1a7d254535">&#9670;&#160;</a></span>AFE</h2>

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<p>bit: 29 Access flag enable </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a805ee3324a333d7a77d9f0d8f0fac9a7">&#9670;&#160;</a></span>B</h2>

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<p>bit: 7 Endianness model </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ac46a564759115a014ad0fcf7c02bd679">&#9670;&#160;</a></span></h2>

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<p>Structure used for bit access. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a122a4dde5ab1a27855ddad88bb3f9f78">&#9670;&#160;</a></span>C</h2>

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<p>bit: 2 Cache enable </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a98b55213f3bf0a8bd4f1db90512238de">&#9670;&#160;</a></span>CP15BEN</h2>

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<p>bit: 5 CP15 barrier enable </p>

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<h2 class="memtitle"><span class="permalink"><a href="#af868e042d01b612649539c151f1aaea5">&#9670;&#160;</a></span>EE</h2>

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<p>bit: 25 Exception Endianness </p>

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<h2 class="memtitle"><span class="permalink"><a href="#afe77b6c5d73e64d4ef3c5dc5ce2692dc">&#9670;&#160;</a></span>FI</h2>

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<p>bit: 21 Fast interrupts configuration enable </p>

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<h2 class="memtitle"><span class="permalink"><a href="#aba2a8aac3478cdc34428af7b9726d97f">&#9670;&#160;</a></span>HA</h2>

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<p>bit: 17 Hardware Access flag enable </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a0a4ed1a41f25a191cf4a500401c3c5db">&#9670;&#160;</a></span>I</h2>

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<p>bit: 12 Instruction cache enable </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a8cbfde3ba235ebd48e82cb314c9b9cc4">&#9670;&#160;</a></span>M</h2>

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<p>bit: 0 MMU enable </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a60d589567422115a14d6d0fde342dfce">&#9670;&#160;</a></span>NMFI</h2>

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<p>bit: 27 Non-maskable FIQ (NMFI) support </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a10212a8d038bb1e076cbd06a5ba0b055">&#9670;&#160;</a></span>RR</h2>

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<p>bit: 14 Round Robin select </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a6598f817304ccaef4509843ce041de1c">&#9670;&#160;</a></span>SW</h2>

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<p>bit: 10 SWP and SWPB enable </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a25d4c4cf4df168a30cc4600a130580ab">&#9670;&#160;</a></span>TE</h2>

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<p>bit: 30 Thumb Exception enable </p>

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<h2 class="memtitle"><span class="permalink"><a href="#abc3055203ce7f9d117ceb10f146722f3">&#9670;&#160;</a></span>TRE</h2>

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<p>bit: 28 TEX remap enable. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a1ca6569db52bca6250afbbd565d05449">&#9670;&#160;</a></span>U</h2>

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<p>bit: 22 Alignment model </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a32873e90e6814c3a2fc1b1c79c0bc8c8">&#9670;&#160;</a></span>UWXN</h2>

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<p>bit: 20 Unprivileged write permission implies PL1 XN </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a9a3885d0e2ba2433d128f62ec2552a00">&#9670;&#160;</a></span>V</h2>

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<p>bit: 13 Vectors bit </p>

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<h2 class="memtitle"><span class="permalink"><a href="#af29c170c65dd4d076b78c793dc17aa0a">&#9670;&#160;</a></span>VE</h2>

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<p>bit: 24 Interrupt Vectors Enable </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a4cb084e09742794f1d040c4e44ee4e0f">&#9670;&#160;</a></span>w</h2>

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<p>Type used for word access. </p>

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<a id="a551d0505856acaef4dd1ecca54cb540d" name="a551d0505856acaef4dd1ecca54cb540d"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a551d0505856acaef4dd1ecca54cb540d">&#9670;&#160;</a></span>WXN</h2>

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<p>bit: 19 Write permission implies XN </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a37f6910db32361f44a268f93b9ff7b20">&#9670;&#160;</a></span>Z</h2>

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<p>bit: 11 Branch prediction enable </p>

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